1. Field of the Invention
The present invention generally relates to a digital-to-analog converter circuit, which may be used in a variety of applications, including image processing.
2. Description of the Prior Art
FIG. 1 is a circuit diagram of a conventional current-type digital-to-analog converter (d/a converter). The d/a converter includes a plurality of subcircuits 10, each of which comprises a switch 12 and a reference current source 14 connected in series. A first terminal of each switch 12 is connected to a respective reference current source 14, and all of the switches 12 in the subcircuits 10 are commonly connected at their second terminals to the output terminal OUT. Switches 12 are selectively turned on and off by the application of various combinations of digital input signals (see FIG. 2 DATA. input). The current value of each current source 14 is predetermined and the summation of these currents is taken out as the analog output voltage produced across load resistor 16.
A conventional d/a converter comprising reference voltage generating circuits and p-channel MOS transistors will now be described with reference to FIG. 2. In FIG. 2 a plurality of digital-to-analog circuits 18-1, 18-2, and 18-3 are connected to a reference voltage generating circuit 20. Each digital-to-analog circuit has a plurality of subcircuits 22, each comprised of a current source 24 and a switching transistor 26. The circuits receive a digital input DATA which controls the switching transistor 26 and provide an analog output either 0 current or some predetermined value of current. The currents are summed and outputted at terminal OUT as the analog output.
The predetermined current which flows through each subcircuit 22 is determined by current mirror circuits which are comprised of transistor 28 respectively combined with transistor 24 in each subcircuit 22. Transistor 28, the reference voltage transistor, operates as an input element of the current mirror circuit and transistor 24, the current source transistor, operates as an output element. Thus, a number of current mirror circuits are formed with the single transistor 28 operative as the reference voltage transistor in each of the circuits. A reference voltage VREF is provided for the current mirror circuits using voltage source E. Transistor 28 of reference voltage generating circuit 20 is connected to respective d/a circuits 18-1, 18-2, and 18-3 by wiring which introduces additional wiring resistance and capacitance. The wiring resistance and capacitance is indicated by resistances 54 and 56 and the additional capacitance is indicated by capacitances 34 and 36.
When the above described conventional current mirror circuit is applied to CRT image processing, three d/a converters, i.e., 18-1 through 18-3, are used for RGB. To generate a reference voltage VREF for each of the d/a converters, only a single transistor 28 of reference voltage generating circuit 20 is employed. The use of but a single transistor 28 in connection with current sources 24 has disadvantages when used with the plurality of d/a converters 18-1 through 18-3.
In FIG. 2 the conventional circuit is shown with the reference voltage generating circuit 20 set apart and separate from the d/a converters 18-1 through 18-3. The reference voltage generating circuit 20 includes the reference voltage generating P-channel MOS transistor 28, an operational amplifier 30, and a resistor 32. This is a normal pattern layout for such a circuit. Therefore, reference voltage generating transistor 28 is located at a distance from the reference current source transistors 24 within each of the d/a converters 18-1, 18-2, and 18-3. Also, transistor 28 is powered, because of its location, from power source E through different power source lines than for transistors 24. As a consequence, the wiring impedance of the power source line for transistor 28 differs from that of the power source lines for the respective transistors 24, thereby resulting in application of a different power source potential to transistor 28 than to the other transistors 24. The difference in source potential applied to transistors 28 and 24 results in different gate to source voltages VGS. The results of such differences in gate to source voltages VGS is shown in FIG. 3. The values of drain currents IDS for two MOS transistors are shown to be different when the gate to source voltage VGS differs. Since the drain currents IDS must be identical for proper operation of the current mirror circuits, such a difference results in errors in the basic current values generated within the d/a converters 18-1, 18-2, and 18-3.
Because of the above-described problem, in the conventional circuit the output linearity characteristics of the d/a converters 18-1 to 18-3 are adversely affected. FIG. 4 shows as an example an acceptable error range of the d/a converter output level to be plus or minus 1/4 LSB from the ideal characteristic curve 48. This range is shown by lines 38 and 40. The output level of conventional prior art circuits, which are effected by differing line impedances and is shown by curve 44, is shown falling outside the acceptable error range when the value of the d/a converter input data becomes large. On the other hand, the output level of the preferred embodiment of the invention, which eliminates the wiring impedance problem, falls within the acceptable error range across a wider range of d/a converter input data values. This is shown schematically by line 42 which can be contrasted with what a typical characteristic 44 of the prior art is likely to be.